Amplifier system

ABSTRACT

A WIDE DYNAMIC RANGE AUTOMATIC HIGH SPEED DIGITAL GAIN RANGING AMPLIFIER SYSTEM HAVING A PLURALITY OF AMPLIFIER STAGES COUPLED IN CASCADE CIRCUIT RELATIONSHIP, WHEREIN IMPROVED BANDWIDTH IS PROVIDED BY D.C. COUPLING BETWEEN THE SUCCESSIVE CASCADED STAGES TOGETHER WITH A FILTER IN A FEEDBACK PATH FROM THE OUTPUT OF THE LAST CASCADED STAGE TO THE INPUT OF THE FIRST CASCADED STAGE. THE RESPECTIVE OUTPUTS OF THE AMPLIFIER STAGES ARE COUPLED THROUGH A COMMON OUTPUT CIRCUIT TO A COMPARATOR CIRCUIT FOR COMPARISON WITH A PREDETERMINED REFERENCE SIGNAL. SEQUENCING MEANS ARE PROVIDED FOR MOMENTARILY CLOSING SWITCH MEANS IN TIMED SEQUENCE FOR SEQUENTIALLY COUPLING THE RESPECTIVE OUTPUTS OF THE SUCCESSIVE AMPLIFIER STAGES TO THE COMPARATOR CIRCUIT DURING SUCCESSIVE, RELATIVELY BRIEF SAMPLING TIME INTERVALS. MEANS ARE PROVIDED FOR SELECTIVELY MAINTAINING ONE OF THE SWITCH MEANS IN ITS CLOSED POSITION FOR A HOLDING TIME INTERVAL OF LONGER DURATION THAN THE SAMPLING TIME INTERVAL WHEN AN OUTPUT SIGNAL COUPLED THROUGH SAID SWITCH MEANS TO THE COMMON OUTPUT CIRCUIT DURING ONE OF THE SAMPLING INTERVALS BEARS A PREDETERMINED RELATIONSHIP TO THE REFERENCE SIGNAL. IN A PREFERRED EMBODIMENT OF THE AMPLIFER SYSTEM, THE COMMON OUTPUT CIRCUIT IS COUPLED TO AN ANALOG-TO-DIGITAL CONVERTER AND THENCE TO DIGITAL RECORDING MEANS FOR RECORDING SIGNALS CORRESPONDING TO BOTH THE INSTANTANEOUS DIGITAL VALUE OF THE SIGNAL AT THE COMMON OUTPUT CIRCUIT AND THE GAIN LEVEL TO WHICH THE SIGNAL IS AMPLIFIED, AS DETERMINED BY THE ONE OF SAID SWITCH MEANS SELECTIVELY MAINTAINED CLOSED TO PASS THE SIGNAL TO THE ANALOG-TO-DIGITAL CONVERTER.

D. L. HOWLETT AMPLIFIER SYSTEM Feb. 9, 1971 'l0 Sheets-Sheet 1 FiledDeo. 24, 1968 T1 'iglllllul Feb. 9, g n. L. HowLETT 3,552,744

AMPLIFIER SYSTEM Filed Dec. 24, 1968 10 Sheets-Sheet s Fek 9, 97 D. L.Hom/LETT 3,562,74

AMPLIFIER SYSTEM Filed Dec. 24, 1968 1o sheets-sheet D. l.. HOWLETTAMPLIFIER SYSTEM Feb. 9, i971 Filed nec. 24, 1968 10 Sheets-Sheet 5 11T@@L wm n. L.. Hom/LETT 3,562j@ AMPLIFIER SYSTEM Filed Dee. 24, 196e 1osheets-sheet s D L HOWLETT 39562,? :L: AMPLIFIER SYSTEM 10 Sheets-Sheeta /Lf//f `l 7 I 0C I /oc/e 2 s w l i I l l f M w 5W Y M, M Flu mi r M@ fW A N RII Mb Y 7%. /a A' 6 e 0 .n w. P e a 8 Y 2 me e Mh, hll H n H Z 11f .m 71 n 7 4. .u Vu] 9 2 7 m a f .fllrllrllr llllllll Il .l c. fm M A M.f 9, e r |L a fa o d I l I I I I l t l I I III ID e e l F. m

D. L. HOWLETT AMPLIFIER SYSTEM Feb. 9, 1971 l0 Sheets-SheetI 9 FiledDeo. 24, 1968 l l l fl Feb. 9, 1971 D. 1 HowLETT AMPLIFIER SYSTEM FiledDec. 24, 1968 T1c1. De/017' /Fnpeoa//ce United States 3,562,744 AMPLIFERSYSTEM Donald lL. Howlett, Houston, Tex., assignor to Texaco Inc., NewYork, NX., a corporation of Delaware lFiled Dec. 24, 1968, Ser. No.786,569 Int. CL H03k 13/02 U.S. Cl. 340-347 45 Claims ABSTRACT F THEDISCLOSURE A wide dynamic range automatic high speed digital gainranging amplifier system having a plurality of amplifier stages coupledin cascade circuit relationship, wherein improved bandwidth is providedby D.C. coupling between the successive cascaded stages together with afilter in a feedback path from the output of the last cascaded stage tothe input of the first cascaded stage. The respective outputs of theamplifier stages are coupled through a common output circuit to acomparator circuit for comparison with a predetermined reference signal.Sequencing means are provided for momentarily closing switch means intimed sequence for sequentially coupling the respective outputs of thesuccessive amplifier stages to the cornparator circuit duringsuccessive, relatively brief sampling time intervals. Means are providedfor selectively maintaining one of the switch means in its closedposition for a holding time interval of longer duration than thesampling time interval when an output signal coupled through said switchmeans to the common output circuit during one of the sampling intervalsbears a predetermined relationship to the reference signal. In apreferred embodiment of the amplifier system, the common output circuitis coupled to an analog-to-digital converter and thence to digitalrecording means for recording signals corresponding to both theinstantaneous digital value of the signal at the common output circuitand the gain level to which the signal is amplified, as determined bythe one of said switch means selectively maintained closed to pass thesignal to the analog-to-digital converter.

The present invention relates generally to amplifier networks featuringbroad bandwidth characteristics and which are suitable for wide dynamicrange amplifier systems; and, more particularly, to automatic high speedgain ranging amplifier systems capable of handling wide 4dynamic rangesignals, such as those encountered in seismic data processing and,therefore, is particularly suitable for use in digital seismic recordingsystems.

The development of wide dynamic range digital seismic field recordinginstruments, having the ability to record seismic data in digital formon high speed magnetic tapes, has brought about the need for precisegain, low distortion analog amplifiers. Such amplifiers are requiredbetween the geophones and the analog-to-digital converters of suchsystems in order to faithfully reproduce the seismic signals at anamplitude level acceptable to the analog-to-digital converter. Thismakes it possible to realize the full dynamic measuring range of thesystem. Advantageously, such systems should have `broad bandwidthcharacteristics.

Since seismic signals may conventionally have a wide dynamic range, sayof the order of 120 db, it has often been the practice in the past tocompress such signals, typically to 78 db, so that they can be processedby the analog-to-digital converter and recorded. Various gain controldevices have been utilized to accomplish such compression, for example,programmed gain control wherein the gain is slowly changed betweenpreset limits as the average seismic signal amplitude changes. Anotherexample of a typical automatic `gain control system involves timeaveraging of the amplified seismic energy to adjust the gain. Morerecently, amplifiers have been developed which provide step gain changesbased on some aspect of signal amplitude existing in a time window ofthe seismic record. One type of amplifier system providing step gainchanges is commonly known as the binary gain amplifier, for example,such as those shown in U.S. Pats. 3,308,392-McCarter; and3,315,233-Hibbard et al. Amplifier systems utilizing step gain changesare also shown in U.S. Pats. 2,967,292-Eisnerg 3,241,100-Loofrbourrowand 3,264,574-Loofbourrow.

The present invention is directed principally to improvements in thebandwidth characteristics of cascaded amplifier network, and isparticularly directed to such improvements for step gain controlamplifier systems capable of handling a wide dynamic range of signalsand providing automatic gain ranging, such as those disclosed in anapplication for U.S. Letters Patent for Amplifier System, filedconcurrently herewith in the name of J ames R. Vanderford. One of theprincipal objects of the present invention is to provide such a widedynamic range automatic high speed digital gain ranging amplifier system-which automatically sets the optimum gain with precision based upon theinstantaneous amplitude of the input at the time the analog-to-digitalconversion is initiated, and which features improved bandwidthcharacteristics.

SUMMARY OF THE INVENTION Briefly stated, one aspect of the presentinvention involves the provision of a cascaded amplifier network of thetype wherein various output paths at different gain levels are providedat selected stages of the network and wherein means are provided forextending the bandwidth of the network comprising the provision of D.C.coupling between the successive cascading stages and a feedback pathfrom the Output of the last cascaded stage to the input of the firstcascaded stage. The invention is particularly suited to provide a widedynamic range automatic high speed gain ranging amplifier systemcomprising a cascaded amplifier network including a plurality of D.C.coupled amplifier stages provided with a feedback path from the outputof the last cascaded stage to the input of the first cascaded stage andmeans for deriving outputs from successive stages of the network forestablishing a plurality of progressively different predeterminedamplifier gain ranges for said network. Advantageously the feedback pathincludes a filter having a high frequency roll-off characteristic and again of at least unity. Means are provided for sequentially switchingfrom one to another of said gain ranges during successive samplingintervals while signals are being translated through said network to acommon output and which includes means for comparing signals translatedto said common output with a predetermined reference signal and forselectively maintaining a predetermined one of said gain ranges during aholding time interval significantly longer than said sampling intervalswhen the output signal translated to the common output bears apredetermined relationship to said reference signal. In a preferredembodiment, the means for establishing said progressively different gainranges comprises means for selectively switching the respective outputsof said cascaded stages to the common output circuit during the samplingintervals and the means for selectively maintaining one of said gainranges comprises means for selectively maintaining one of said cascadedstage outputs coupled to said common output during the holding timeinterval.

Advantageously, in accordance with a preferred aspect of the invention,the common output circuit is coupled through an analog-to-digitalconverter to a digital recording means for recording signal informationcorresponding to the instantaneous digital value of the signal at thecommon output circuit and the gain level at which the signal is beingtranslated through the system, as determined by which one of theamplifier gain ranges is being maintained during the holding intervalWhile the signal is being coupled to the common output circuit.

In accordance with a further aspect of the invention a plurality of saidgain ranging amplifier systems are provided, together with multiplexingmeans for coupling the respective outputs thereof on a time shared basisto means comprising the analog-to-digital converter.

In a preferred embodiment the wide dynamic range amplifier systemcomprises part of a seismic data processing system including means forsupplying seismic signal information to the input of the amplifiersystem.

In a preferred embodiment the feedback signal and incoming signal areapplied to a stage of amplification having an amplification factor of 2,with appropriate networks providing attenuation of the respectivesignals of 1/2, so that the stage has a net gain of unity.

Advantageously, the feedback network includes an active filter having again of at least unity and a high frequency roll-off characteristic.

The objects and advantages of this invention may be better understoodand appreciated by referring to the detailed description set forthbelow, together with the drawings in which:

FIG. la is a schematic circuit diagram, partly in block form, showing aseismic data processing system incorporating a plurality of wide dynamicrange automatic high speed gain ranging amplifier systems, in accordancewith the present invention.

FIG. lb is a schematic circuit diagram, partly in block form,illustrating another embodiment of the present in vention incorporatedin a seismic data processing system like that of FIG. la.

FIG. 1c is a schematic circuit diagram, partly in block form,illustrating in further detail a portion of the systems shown in FIGS.la and 1b, especially that portion of the respective systems identifiedas element I in FIGS. la and 1b.

FIG. 2a is a schematic circuit diagram, partly in block form,illustrating another form of a seismic data proc essing systemincorporating a plurality of wide dynamic range high speed amplifiersystems in accordance with the present invention.

FIG. 2b is a schematic circuit diagram, partly in block form,illustrating another embodiment of the invention incorporated in aseismic data processing system like that of FIG. 2a.

FIG. 2c is a schematic circuit diagram, partly in block form,illustrating in further detail a portion of the systems shown in FIGS.2a and 2b, especially that portion of the respective systems identifiedas element I' in FIGS. 2a and 2b.

FIG. 3 is a schematic circuit diagram, in block form, illustrating infurther detail the portions of the system of FIGS. 1a, lb, 2a and 2bidentified as Detail A.

FIG. 4 is a schematic circuit diagram, partly in block form,illustrating in further detail the portions of the systems of FIGS. la,1b, 2a and 2b identified as Detail B.

FIG. 4a is a diagrammatical representation showing the characteristicfrequency response of the cascaded circuit networks shown in FIGS. la,1b, 2a and 2c, including the Detail O feedback loop of the respectivecascaded network.

FIG. 5 is a schematic circuit diagram illustrating in further detailthat portion of the systems of FIGS. la, 1b, 2a and 2b identified asDetail C.

FIG. 6 is a schematic circuit diagram, partly in block form,illustrating in further detail that portion of the systems shown inFIGS. la, lb, 2a and 2b identified as Detail D.

FIG. 6a is a schematic circuit diagram, partly in block form,illustrating an alternative and preferred form of the portion of thesystems shown in la, 1b, 2a and 2b identified as Detail D and whichalternative form is identified in FIG. 6 as Detail D.

FIG. 7 is a schematic circuit diagram, in block form, illustrating infurther detail that portion of the systems shown in FIGS. la, lb, 2a and2b identified as Detail E.

FIG. 8 is a schematic circuit diagram, in block form, illustrating infurther detail that portion of the systems shown in FIGS. la, 1b, lc,2a, 2b and 2c identified as Detail F.

FIG. 9 is a diagrammatical representation of the amplitude of a signalafter amplification, illustrating the characteristics of one example ofan amplifier system constructed in accordance with the principles of thepresent invention.

FIG. 10 is a schematic circuit diagram, partly in block form,illustrating in further detail those portions of the systems shown inFIGS. la, 1b, 2a and 2b identified as Detail O (comprising Detail M andDetail N) and that portion of the systems shown in FIGS. la and 2a asDetail B12 FIG. l1 is a diagrammatical representation showing in dashedline a plot of possible tilt errors `which may occur at the output ofany given cascaded stage of the amplifier network illustrated in FIGS.la through 2c, when not provided with D.C. coupling and a feedback pathin accordance with the present invention, and showing the correspondingoutput in solid line provided in accordance with the present invention.

FIG. 12 is a diagrammatical representation showing the characteristicresponse of the amplifier network feedback stage, identified as Detail0, provided in accordance with the present invention.

FIG. 13 is a schematic circuit diagram, partly in block form,illustrating in further detail that portion of the systems shown inFIGS. lb and 2b identified as Detail P.

The systems shown in FIGS. la and 1b are substantially identical exceptfor the circuit arrangement for returning the feedback path, includingDetail 0, to the input of the cascaded amplifier stages. In FIG. la thefeedback path is applied to the input of the first cascaded stage B1',which is modified as shown in FIG. 10, so that the feedback signal isinserted at one end of resistor R2. This differs from the other cascadedstages, shown as Detail B, wherein the corresponding end of the resistorR2 is directly coupled to common ground. In the system shown in FIG. 1b,the feedback path including Detail O is applied to the input of thefirst cascaded stage B1 through the intermediatory of an additionalstage, identified as Detail P, as illustrated in FIG. I3 and describedfurther hereinafter.

The distinctions between the systems shown in FIGS. 2a and 2b aresimilar to the distinctions described above as between FIGS. la and 1b.

In FIG. la, there is shown a seismic signal processing and recordingsystem, including a plurality of geophones, g1, g2, gn, indicating thepresence of a plurality of such acoustic-to-electric transducing devicesas determined by the particular practice in the art, for example, 12 or24, or some other number thereof. Each of these geophones may, inactuality, comprise a group or cluster of a plurality of individualgeophone instruments, with their respective outputs coupled together toprovide a common geophone signal.

It is conventional practice in seismic surveying to employ a pluralityof such geophones at successive distances from a source of seismicenergy located at a shot point to detect acoustic energy arriving fromthe source over different travel paths during measured time intervalsand to display signals representing the outputs derived from therespective geophones as adjacent traces along a time base reference. Inaccordance with the hereinafter disclosed system, signal informationcorresponding to the geophone output signals are amplified in respectivesignal channels, converted from analog-to-digtal form and recorded onmagnetic tape. Such tape recorded signals can, if desired, bereproduced, reconverted to analog form and recorded in trace form, asdisclosed. However, of more importance is the fact that such digitallyrecorded signals can be subjected to modern data processing techniquesusing high speed digital computers and related equipment.

The amplifier system herein disclosed offers the further advantage ofproviding an output signal which can be recorded in fioating point form,e.g. as a digital Word comprising a mantissa and an exponent, asdescribed in further detail hereinafter, which accurately represen-tsthe absolute value of the input signal corresponding thereto. Byrecording such fioating point signals on magnetic tape it is possi-bleto preserve not only the relative values but also the absolute values ofthe amplified signals.

In FIG.V la, the respective geophones g1, g2, and g11 Y are showncoupled to the input portions of respective signal channels identifiedas channels `1, 2 and n, respectively. Each of these signal channels aresubstantially identical, with corresponding elements thereof beingidentified by the same reference numerals or letters, as the case maybe. While three channels are shown in the illustrated embodiment, it isto be understood that channel n is representative of one or more suchchannels and that, in most cases, seismic'signal processing systems ofthe type described will comprise twelve, twenty-four, or a larger numberof channels.

Each of channels 1 through n comprises a plurality of amplifier stages,A and B1 through B4, directly coupled, eg. D.C., coupled to one anotherin cascade circuit relationship, together with associated circuitryincluding a common output circuit and means for selectively coupling theoutput of one of the amplifier stages at a time to the common outputcircuit when the signal at the output of said one of the amplifierstages corresponds to a predetermined reference potential whensequentially sampled in a manner hereinafter described in detail. Afeedback circuit, including the circuit elements within the dashed boxidentified as Detail 0, is provided from the output of the last cascadedstage B1 to the input of the first cascaded stage B1. The circuitdetails and functions of the feedback path will be describedhereinafter, with particular reference to FIG. showing the elements ofDetail O and Detail B1.

Each of the amplifier channels, e.g. each of the amplifier systemscomprising channels 1 through n, is shown coupled in a seismic signalprocessing and recording system including means hereinafter to bedescribed whereby the outputs of the respective channels 1 through n aremultiplexed on a time sharing basis so that the signals of therespective geophones g1 through gn may be processed and coupled to ananalog-to-digital converter and thence to a digital tape recorder (notshown).

Referring particularly now to the details of that portion of FG. lacomprising channel 1 thereof, it is seen that the output of the geophoneg1 is coupled to the input of the channel 1 input circuitry,schematically shown as the block A, further illustrated in FIG. 3 asDetail A, and which comprises a suitable input circuit such as an inputtransformer, a precision gain preamplifier, seismic filters, high linebalance, seismic alias filter and logic gates to interrogate the inputattenuator switch and precision gain stage A1 and generate a binarycoded signal to represent the overall gain of this stage or section ofthe system, in a manner described in further detail hereinafter. Thecombination of the input attenuator of the input electronic section,identified as Detail A, and the precision gain preamplifier thereof arenormally adjusted manually to give an overall predetermined gain toDetail A, as determined by the operation of the system to be discussedin detail hereinafter. However, in a preferred embodiment the gain ofDetail A should be bk, so that k can be added to (or subtracted from)the exponent determined by the following stages of the channel. Oneembodiment of this system uses a Value of k equal to unity (k=l.000 and11:8). The output of the channel 1 input section A is shown coupleddirectly to the input of the first of a series of cascaded precisiongain amplifier stages, schematically shown as blocks B1 through B4, eachof which is further illustrated in FIG. 4 as Detail B (it is noted thatthe first cascaded stage `B1 of FIGS. la and 2a, respectively, isconnected in circuit as shown in FIG. 10, within the dashed box labeledDetail B1 of FIGS. la and 2a, as described hereinafter) and whichprovides both alternating current (AC.) and direct current (DC.)amplification of a selected base value b to the exponent k. By way ofexample, in one embodiment b=8 and k=l.O00, such that bk=8.i0'00, forboth alternating current (AC.) and direct current (DC.) amplification.Each of the precision gain amplifier stages B1 Vthrough. B4 arenoninvertng wideband amplifier stages, the gain of which may be set byprecision resistors in the feedback loop thereof, as describedhereinafter.

Each of the precision gain amplifier stages B1 through B1 is shown withits input circuit coupled to a respective constant voltage sourceschematically shown as blocks C1 through C4, as the case may be, each ofwhich is further illustrated in FIG. 5 and Detail C. Each of y thevoltage sources, C1 through C4, provides both positive and negative D.C.reference voltages, and includes appropriate means known to thoseskilled in electronics for limiting the input of the succeedingprecision gain stage for the purpose of preventing large signaloverloads and distortion therein. Constant voltage sources C1 through C4are described in further detail hereinafter. It is to be understood thatalthough a constant voltage source is shown serially connected in theinput circuit of each of the precision gain amplifier stages, it iscontemplated that the `function of the constant voltage sources, e.g. toprotect the respective amplifier from overloading, can be achieved byappropriate design of the amplifier per se.

Coupled to the output of the input electronics, Detail A, including theprecision gain preamplifier thereof, and likewise coupled to therespective outputs of each of the succeeding amplifier stages,identified as B1 through B1 of the cascade circuit arrangement, there isprovided a respective bandwidth determining device schematically shownas blocks D1 through D5 respectively, each of which is furtherillustrated in FIG. 6 as Detail D and which comprises a phasecompensation device, a gain calibration device which can either amplifyor attenuate with precision, and an impedance transformer. In oneembodiment of the amplifier system, each of the bandwidth determiningdevices .D1 through D5 may include means for removing the DC. componentfrom the signal. Each of the devices D1 through D5 also includes circuitcomponents which function as an isolation stage separating therespective outputs of the amplifier stages B1 through B1 from the signalinput of a corresponding switching network schematically shown as theblocks E1, E2, E5, E1, E5, as the case may be, each of which is furtherillustrated in FIG. 7 as Detail E. ln summary, therefore, each of thebandwidth devices, D1 through D5, respectively, is shown having itsrespective output coupled to one of the corresponding switching networksE1 through E5.

Each of the bandwidth determining devices, D1 through D5, also includesmeans for adjusting it to the appropriate D.C. level of the commonoutput of all switches, i.e. of the switching networks E1 through E5into which the outputs of the bandwidth devices D1 through D5 arecoupled or fed.

The bandwidth determining devices D1 through D5 provide means foradjusting the bandwidth of the various circuit paths from the input of aparticular amplifier channel to the common output, e.g., for equalizingthe successive signal paths from the input of Detail A through therespective electronic switch networks E1 through E5 to the common outputcomprising Detail F, so that the bandwidths of these various paths areequalized. Preferably the various bandwidths of all paths correspond tothat of the longest path, which is the path through the last of thecascaded amplifier stages, namely, that including devices yB4 and switchE5, as shown in FIGS. la, 1b, 2a and 2b.

In addition to bandwidth, these devices D1 through D5 also provide meansfor adjusting the phase of the Various signal paths so that they conformto the phase of the longest path as described above. It will beappreciated that when using linear circuit elements phase equalizationof the various paths will also amount to bandwidth equalization thereof.

The circuitry comprising the successive Detail D portions of the circuitalso act as isolation stages to keep the switching transients of therespective Detail E switching networks out of the input of the nextfollowing cascaded amplifier comprising Detail B of the system.

It will be appreciated that, in the illustrated embodiments, the lastbandwidth determining device D5, coupled between the output of the lastof the cascaded amplifier stages B4 and the last of the switchingnetworks E5, is not essential from the standpoint of preventingswitching transients from infiuencing the next following cascadedstages, since there are no further cascaded stages to be effected by thelast bandwidth device D5. Moreover, the last bandwidth device D5, whileuseful in equalization of bandwidth and phase, is not essential for thatpurpose in the context of the disclosed system inasmuch as the shortercircuit paths including preceding bandwidth devices D1 through D4 can beadjusted to correspond to the bandwidth of the longest circuit pathincluding the last cascaded amplifier B., and the last switching networkE5.

The circuitry comprising the last device Detail D5 is neverthelessuseful in the illustrated embodiments to provide means for adjusting thevarious amplifier output paths to the D.C. level of the common output ofall switches and is preferably employed for that purpose.

The foregoing discussion concerns the circuit described as Detail D,shown in FIG. 6. However, it is to be understood that in accordance withthe preferred embodiments of the invention, featuring improved broadbandwidth, characteristics, significant advantages are to be obtained bythe use of the circuit illustrated in FIG. 6a, identified as Detail D,rather than the circuit discussed above and identified as Detail D.

In the circuit of FIG. 6a, it is seen that the Detail D circuitcomprises an operational amplifier of the non-phase inverting type,which is of the normally open input type which provides no D.C.blocking. Thus, this a direct coupled D.C. amplifier, as distinguishedfrom a ciro cuit such as Detail D, shown in FIG. 6, which is providedwith a series input capacitor C2 which provides D.C. blocking.

The use of the Detail D' configuration shown in FIG. 6a assures theprovision of a D.C. circuit path for each of the outputs derived fromthe successive stages of the cascaded circuit network. This assures,together with the Detail LO feedback loop, that the amplifier providesbroad bandwidth characteristics, down to direct current.

Each of the switching networks E1 through E5 comprises a high speedelectronic switch network including; firstly, one or more input logicgates for external signaling of on and off times; secondly, a switchingdevice, preferably in the nature of a field effect transistor (FET);and, thirdly, a driver circuit for translating the input on and offsignals into signals which activate the appropriate field effecttransistor switch.

The respective outputs of each of the switching networks E1 through E5are shown coupled to the input of a high speed amplifier and impedancetransformer schematically shown as the block F, further illustrated inFIG. 8 as Detail Ff Thus, it is noted that the input ofamplifier-transformer F is a common connection for the respectiveoutputs of all of the switching networks, El

through E5, with respect to each channel and, in fact, with respect toall channels in the embodiments illustrated in FIGS. 1a and 1b of thedrawing where one arnplifier-transformer F is provided in common for theentire amplifier system, e.g., with all channels thereof being connectedto the input of the same high speed amplifier and impedance transformerF.

Amplifier-transformer F has a relatively higher input impedance,preferably of the order of 10'7 times the on resistance of the fieldeffect transistor switch output of the respective switching network Elthrough E5 coupled to the input thereof. In a preferred embodimentutilizing a follower type amplifier stage, the output impedance of theamplifier-transformer F is essentially zero (O) and the gain thereof isnormally unit (+1.000).

Thus, it is seen that in each channel the respective outputs of each ofthe cascaded amplifiers in the series circuit comprising thepre-amplifier of Detail A and the succeeding precision gain stages B1through B4, are all shown coupled through appropriate circuitryincluding a respective one of the high speed electronic switchingnetworks El through E5 to a common output circuit comprising the inputof the high speed amplifier-transformer circuitry F. Moreover, in theembodiments of FIGS. la and 1b, the respective outputs of each of theamplifier channels, e.g. channels 1 through n, are shown coupled to theinput of the same high speed amplifier and impedance transformer F,whereby there is thus provided a common output circuit for all channelsof the entire seismic System.

It is noted that a combination of any number of the aforementioned highspeed switch networks, such as El through E5, together with a singlehigh speed amplifier and impedance transformer, such as F, constitutesin the disclosed circuitry, including scanning means to be further udescribed hereinafter, a high speed multiplexer or commutator in whichrelatively inexpensive switch components, eg. field effect transistorswith non-precision on resistance can be used, one of the principaladvantages being that the switches can be replaced without recalibratingthe amplifier paths.

The output of the amplifier-impedance transformer F is shown coupled tothe respective inputs of first and second digital decision devices,schematically shown as the blocks H and I, respectively, which serve thefunction of determining when the output amplitude of theamplifier-impedance transformer F exceeds either the positive (device H)or negative (device I) reference potentials (+V or -V), schematicallyidentified in the drawings, supplied by a source schematically shown asthe Block G.

The digital decision devices H and I are known circuits of the typegenerally classified as Voltage Comparators, for example, as describedon pages and 46 in Handbook of Operational Amplifier Applications,published by Burr-Brown Research Corporation, Tucson, Ariz., 1963.Device G is a know circuit of the type found on page 49 of the abovereference.

The reference voltage source G is a precision source having two outputs,one being a positive voltage is supplied to the device H and the otherbeing a negative voltage is supplied to the device I. Both of thereference voltages supplied by the source G are predetermined such thatwhen the output signal provided by the amplifierimpedance transformer Fat any given instant and coupled to the digital decision devices H andI, respectively, exceeds in amplitude either the predetermined positivevoltage or predetermined negative voltage, as the case may be, then acomparison signal is supplied by the appropriate decision device H or Ito a Digital `Control and Multiplexer Network schematically shown as theblock I, further illustrated in FIG. la as Detail 1, and which, in turn,controls the control input of the appropriate high speed electronicswitch network, e.g. appropriate Detail E then in the closed orconducting condition and then passing the signal under comparison sothat said switch will remain closed for the duration of a sampling cycleto provide the analog-to-digtal sample-hold measurement in a mannerhereinafter to be described in further detail.

The Digital Control and Multiplexer Network J functions as a programmerfor the high speed switches E1-E5. The network or programmer responds toa synchronizing signal, i.e. to a sync or go pulse transmitted theretoover the sync input channel from an appropriate digital clock, e.g. thesync pulse shown coupled thereto from the Analog-Digital Converter. Inresponse to such a sync or go pulse, the programmer I functions to tumon in timed sequence the successive high speed electronic switches E1through E5. The system may be operated to scan either up or down thesequence of switches, e.g. from E1 to E5 or from E5 to E1. The preferredmode of operation is to be discussed hereinafter. Let us assume that thesystem is programmed to scan the respective switches E1 through E5 ofchannel 1, for example, thereafter going through the succeeding channels2 to lz. In the course of, scanning channel 1 let us assume that theswitch E1 is turned on by the action of the control signal S1 from thedigital Control Network I in response to a sync or go pulse from theAnalog-Digital Converter and Control Logic. At that instant, a signalapplied to the input of the geophone g1 is translated through the inputelectronics A, thence, through the band-width determining device D1thence, through the then closed switch network E1 to the common outputcomprising the input to the amplifierimpedance transformer,schematically shown as the block F, which, in turn, applies a signalsimultaneously to the two digital decision devices H and I,respectively, which function to compare said applied signal with thepositive and negative reference signals, -l-V and -V, provided theretoby the precision voltage source G. If the signal applied exceeds inamplitude either the positive reference voltage, -l-V, applied to H, orthe negative reference voltage, -V, applied to I, as the case may be,the scanning operation controlled by the digital control network orprogrammer I, is effectively halted or stopped with electric switchnetwork E1 maintained or held in a closed position during the remainderof the cycle so that the output signal coupled through said switch maybe translated through the amplifier-transformer F to the Analog-DigitalConverter and Digital Control Logic shown coupled to the output thereof,the operation of which will be further discussed hereinafter.

Returning to the operation of the digital control network or programmerI, unlike the aforementioned situation, let us assume that switchnetwork E1 is momentarily closed in response to a signal from thedigital network J and that the output of the amplifier-impedancetransformer F does not exceed either the positive or negative referencepotentials, +V or -V, supplied by precision source G to devices H or I,respectively, then the digital network I will function to turn ofi e.g.open the switch network E1 and turn on the next succeeding electronicswitch E2. The signal translated to the second switch network E2 willthen be tested in the same manner as the signal that was suppliedthrough the first switch network E1, e.g. the same comparisons will bemade with the positive and negative reference potentials, +V and -V, todetermine whether or not the programmer J should hold or lock on to thesecond switch network E2 in the closed condition or continued throughthe cycle testing, in turn, the following switch networks E3 through E5until a signal exceeding the positive or negative reference potentialssupplied through one of the switching networks E1 through E5 by way ofthe amplifier-transformer F to the respective decision devices H and I.In the event that these conditions are not satisfied through the cycle,c g. that the control network I momentarily closes E1 through E5, inturn, without providing a signal to H or I that exceeds thepredetermined reference potentials -l-V or -V, then the cycle will stopwith the fifth switch network E5 in a closed position. The cycle willbegin again in response to the next sync or go pulse transmitted to thedigital control network I. In accordance with a preferred embodiment thetime required for a decision on any switch connection is a minimum of1/2 microsecond.

Associated with each sync or go pulse transmitted to the digital controlnetwork I there is provided a second signal, a channel number pulse,which selects a set of switches on a particular channel, eg. one ofchannels 1 through n in sequence.

The Digital Control and Multiplexer Network I also contains the ExponentAdder and means for gating signals corresponding to three exponentdigits K1, K2 and K3 to the digital recorder. The exponent digit signalsK1, K2 and K3 are shown on the output connection coupled from thecontrol network J to the analog-to-digital converter, designated ADConverter and Dlgital Control Logic Vin the drawings, where they aresupplied to the tape writing circuits of the digital tape recorder (notshown). The exponent digit signals K1, K2 and K3, provide information tothe analog-to-digital converter identifying the gain level of theamplifier system, as determined by the gain of Detail A and by which oneof the electronic switch networks E1 through E5 translates a particularsignal being recorded in digital form. Otherwise stated, the signalsupplied by the common output circuit including the amplifier andirnpedance transformer F to the analog-to-digital converter provides thevalue of the translated signal within a given range level, e.g.mantissa, and the exponent digits show the amplification range Or level,e.g. exponent, through which that signal was translated and which isdetermined by the condition of the switching devices E1 through E5, onlyone of which is responsible for a given output signal supplied to the ADconverter.

It will be appreciated that by thus writing e.g., recording, a floatingpoint digital number on the magnetic tape carried by the recorder (notshown) in the form of mantissa and exponent this number may be made torepresent the absolute seismic signal amplitude as it appeared at theoutput of the corresponding geophone from which it originated.

It is to be appreciated that the analogtodigital converter includes asample and hold circuit and also a source of real time pulses. Thesample and hold circuit serves to assure sampling of the signal appliedthereto for a sufficient time to make the analog-to-digital conversionfor recording in digital form on an appropriate recorder (not shown)coupled to the AD Converter outputs. The recorder may be any suitabledevice such as a digital tape recorder.

The functions of the Digital Control and Multiplexer Network J may bebetter understood and appreciated by reference to FIG. 1a of thedrawings wherein the elements which comprise the network J are shownwithin the dashed box. In FIG. la the respective outputs of the twoDigital Decision devices, H and I, are shown coupled to an Exclusive ORGate within the Digital Control and Multiplexer Network I. The ExclusiveOR Gate is a known type of circuit responding with an output signal onlywhen the two input signals are digitally unlike. An output signal fromthe Exclusive OR Gate, corresponding to a signal combination fromdecision device H and decision device I is shown coupled to a firstinput, designated Enable 1, of an Amplitude Memory Logic circuit, whichis a known type of circuit consisting principally of' a Set-Reset FlipFlop. The Amplitude Memory Logic circuit is provided with a secondinput, designated Enable 2, to which is applied a timing signal from afirst output of a Time Decode Register, which is a conventional circuitfor performing binary-to-decimal conversions, for example, as describedin Digital Computer Primer, by E. M. McCormick, especially page 135,published by McGraw-Hill Book Company, Inc., New York, 1959 (Library ofCongress Catalog Card No. 58-13011). The Time Decode Register alsoincludes second and third outputs which provide Set and Reset signals,respectively, to

second and third imputs, respectively, of the Amplitude Memory Logiccircuit. The Time Decode Register is programmed by signals coupled toappropriate inputs thereof from corresponding outputs of a Divide By 32Flip Flop Counter which, in turn, is provided with a first input that iscoupled to a constant frequency reference source of timing pulses, shownas a 1.024 megacycle per second clock (designated 1.024 mc./s. clock).The Divide By 32 Flip Flop Counter is also a known type of circuit forproviding 32 possible timing pulses, since it is desired in theillustrated embodiment to provide a nominal 31 microsecond operatingcycle and to be able to choose pulses within nominal one (1) microsecondintervals. The Divide By 32 Flip Flop Counter includes a reset circuit(not illustrated, per se) and is provided with a second input forreceiving Reset signals from a source of go or sync pulses which, asshown in FIG. 1, may be provided by the A. D. Converter and DigitalControl Logic circuit.

The Amplitude Memory Logic circuit is provided with an output showncoupled to a first input designated input #1, of an AND gate, having asecond input designated input #2, coupled to an output of the TimeDecode Register for coupling an Advance Switch Counter Signal to the ANDgate. The AND gate may be a known type of gate circuit for respondingonly to the simultaneous occurrence of appropriate gating signals atinputs 1 and 2 thereof, for providing an output signal which is showncoupled to input 1 of a Switch Counter. The Switch Counter is a knowntype of circuit consisting essentially of a plurality of Flip Flops incascade connection. Input #2 of the Switch Counter is shown coupled to afourth output of the Time Decode 4Register for coupling a Preset signalfrom the latter to the Switch Counter.

The Switch Counter circuit is provided with a plurality of outputs,three (3) being shown, for coupling signals designated X1, X2 and X3representing exponents to three (3) corresponding inputs of the ExponentAdder. The Exponent Adder is also proivded with a plurality ofadditional inputs, three 3) being shown designated Y1, Y2 and Ya, forreceiving signals in binary from corresponding to the overall gain ofDetail A. The Exponent Adder, in turn is provided with three (3) outputpaths which, as shown in FIG. 1, comprise the output paths of theDigital Control Network I for coupling the exponent signals K1, K2 andK2 from the Digital Control Network I to the analog-to-digitalconverter, in order to provide information as to the gain level of theamplifier system, as determined by the gain of Detail A and by which oneof the electronic switch networks E1 through E5 translates a particularsignal being converted and recorded in digital form. The Exponent Adderis a known type device consisting of a plurality of Flip Flops andlogical AND and OR gates whose function is to add and store the digitalsignals presented on the input channels whenever the Add Exponent Signalis activated.

Output signals corresponding to the exponent signals X1, X2 and X3 arealso coupled from the appropriate outputs of the fSwitch Counter, asshown in FIG. 1a, to three corresponding inputs of the Gain Switch Logicand Multiplexer circuitry which, in turn, is provided with appropriateoutput circuits, as shown, for each of channels 1 through n for couplingappropriate channel switching signals S1 through S5 to the appropriateswitching network E1 through E5 of each of channels 1 through n, inorder to control or program the switching networks E1 through E5 of eachof the channels 1 through n, as shown in FIGS. la and 1b.

The Gain Switch Logic and Multiplexer circuit is also provided with aplurality of input circuits for receiving channel number signals coupledthereto from the AD Converter and Digital Control Logic, also as shownin FIGS. la and 1b of the drawings. The function of the channel numbersignals is to correlate or synchronize the functioning of the GainSwitch Logic and Multiplexer so that the channel programming signalsoccur according 12 to desired sequence. The Gain Switch and Multiplexercircuit is a conventional circuit for performing binary-todigitalconversions.

In the apparatus of FIGS. la and 1b, including the Detail I portionthereof illustrated in FIG. lc, multiplexing of the various channelswitching networks E1 through E5 is accomplished by means including theGain Switch Logic which functions to program or control the sequenceaccording to which of the switching signals, S1 through S5, are applied,in turn, to the switching networks E1 through E5 of the respectivechannels 1 through n.

The Gain Switch Logic and Multiplexer is programmed to cycletime-sequentially through all switch networks, E1 through E5, of a givenchannel and then to cycle through the switch networks, E1 through E5, ofthe next channel, and so on through respective channels 1 through n. Inthe illustrated case, the switching proceeds from channel 1 on throughchannel n; however, it is to be understood that the numerical order ofevents may be reversed. In any event, the selection of the sequence ofchannels is determined by the channel number signals applied to theDigital Control Logic and Multiplexer Network which, in turn, iscontroled as a function of the signals provided by the AD Converter andDigital Control Logic illustrated in FIGS. 1a and 1b.

The foregoing detailed description of FIG. la, applies equally to thedescription of the system shown in FIG. 1b, except for the details ofthe feedback circuit including Detail O and associated elements, asdiscussed above and described further hereinafter.

In the system of FIG. la, negative feedback is provided by the feedbackloop including the Detail O active filter, coupled to the input of thefirst cascade amplifier stage B1', which is a modified version of theother cascade amplifier stages of FIG. la, namely, stages B2 through B1,as shown in FIG. 4. The modied cascaded stage B1 is shown in FIG. l0 asbeing identical with the other cascade stages, except for the fact thatthe terminal end of the resistor R2 is coupled to the output of thefeedback loop, e.g. the output of the Detail O filter network, ratherthan being coupled directly to ground as with the other cascade stagesshown in FIG. 4.

The Detail O portion of the feedback loop comprises an active filterhaving a high-frequency roll-characteristic and a characteristic gain ofat least unity. In the illustrated embodiment the Detail O filternetwork is provided with a gain of unity, as determined by the feedbackloop coupling the output terminal of the operational amplifier to thenegative input terminal thereof, as shown in FIG. l0.

As seen in FIG. l0, the Detail O portion of the feedback loop comprisesa Detail N portion, in the form of a network of resistors andcapacitors, the values of which may be selected to provide the desiredfrequency characteristic of the Detail O circuit, together with anactive stage comprising an operational amplifier shown provided with theaforementioned feedback loop from its output end to its negative inputterminal in order to provide the specified unity gain for the activefilter comprising the Detail O circuitry. The Detail O circuitry shouldhave a gain of at least unity, and is shown as a positive gain of unity(+1) in the illustrated embodiment. It is to be understood that anegative gain of at least minus one 1) may be chosen, in which event itwill be necessary to make an appropriate change in the manner ofsupplying feedback to the input of the cascaded network in order toassure injection of the feedback in proper phase relationship with theinput signal.

With particular reference to FIGS. 1b and 2b, which are preferredmodifications of the systems shown in FIGS. la and 2a, respectively, itis seen that the output of the feedback loop including the active filterDetail O is coupled to the input of an additional amplifier stage,Detail P, inserted between the output of the input electronics A and therespective inputs of the constant voltage source 13 C1 and the bandwidth determining device D1 or D1' as the case may be. The details ofthe circuit identified as Detail P and its manner of its connection tothe aforementioned adjacent circuits is shown in FIG. 13, wherein it isseen that the Detail P circuitry comprises means for providing aconstant input impedance regardless of the input signal by isolating theeffect of the constant voltage source C1 on the input electronicscomprising Detail A. Otherwise stated, the Detail P portion of thecircuit provides a low impedance drive to the clipper circuit comprisingthe constant voltage source C1. The Detail P stage comprises anoperational amplifier -with a gain of two (2) in combination with anetwork of resistors for attenuating the gain by a factor of one-half(1/2) so that Detail P has a net gain of unity (l) for signals appliedto each of Vits inputs. It also provides a summing point for introducingthe feedback from Detail O to the input of the cascaded amplifiernetwork along with the signal from the input electronic A.

It is further observed that the Detail O active circuitry shown in FIG.provides substantially 100% negative feedback for D.C. and provides apredetermined A.C. feedback, within its pass band. This allows the gainstages of the cascaded amplifier network to be D.C. coupled throughoutand still have D.C. stability. An important advantage of this circuitover circuits of the type herein described, but without D.C. couplingand the prescribed feedback loop, is that the gain stages of thecascaded amplifier network are actually D.C. amplifiers. For all butvery small signals, some of the gain stage signals will be saturated dueto the diode clipping circuits shown in Detail C. An A.C. amplifier willnot pass such a clipped signal and distortion may result, as illustratedin FIG. 11 by the dashed line X, showing possible tilt errors. The solidline Y illustrates the correction provided by the subject invention, asdescribed by the legend on the drawing.

The response of the feedback filter stage, Detail O, is shown in FIG. 12of the drawing, as having a high frequency roll-off characteristic atf1, which in a preferred embodiment may be of the order of 10-3 to 10-5cycles per second. The solid line in FIG. 12 shows a somewhat idealizedplot and the dashed line a typical actual plot of the response of anembodiment of Detail O, wherein the response is shown rolling-off at avalue approaching 12 db per octave. The roll-off should preferably be atleast 6 db per octave, but less than 12 db per octave, since ringingoscillation may occur at l2 db per octave. In a preferred embodiment thefilter is characterized by an initial roll-off approaching 12 db peroctave, changing to 6 db per octave for about the lower one-third of itsrange. This advantageous combination 12 db-6 db rolloff may be providedby proper selection of R11 shown in FIG. 12, Detail `N, betweencapacitor C4 and ground.

The Detail O feedback filter is thus characterized as a low pass filter,rolling-off at a low frequency, as determined by its pass bandcharacteristic described above and shown in FIG. l1.

It will be appreciated that the prescribed circuit con- 'figuration forthe feedback loop, together with the D.C. coupling provided for thecascaded amplifier stages, eliminates the tendency to tilt for waveforms following the first limited input, as illustrated in FIG. 11. Thenet effect of the application of D.C. coupling and the prescribedfeedback loop is such that the D.C. drift error at each stage output iseffectively the same as the error of each individual stage when it isdisconnected from all other stages.

It is to be appreciated that, although the individual cascaded stageseach have the same gain for both A.C. and D.C., the amplifier networkincluding the negative feedback loop has an overall D.C. gain ofsubstantially unity at the common output circuit, -while providing asignificantly higher A.C. gain, as described in detail elsewhere herein.

Referring now to FIGS. 2a and 2b, there are shown other embodiments ofthe present invention, generally like those of FIGS. la and lb,respectively, except for the means for performing the multiplexingfunctions. In the embodiments of FIGS. 2a and 2b multiplexing isprovided by a common Channel Multiplexer, with programming provided bythe modified Digital Control Network shown as the block J', and which isfurther illustrated in FIG. 2c as Detail J', as described in furtherdetail hereinafter. The embodiments of FIGS. 2a and 2b differ from oneanother in a manner similar to the differences between the embodimentsof FIGS. la and lb, eg. with respect to the feedback path includingDetail 0, which is coupled directly to the negative side of theoperational amplifier of the B1 stage in FIG. la (as shown in FIG.

10), rather than through an additional stage such as Detail P (as shownin FIG. 13).

Whereas the outputs of all of the respective channels 1 through n of theFIGS. la and lb embodiments are coupled to the input of a commonimpedance matching element F, in the FIGS. 2a and 2b embodiments thereis provided a separate amplifier-impedance transformer F for each ofchannels 1 through n. The respective outputs of each of the separateimpedance matching circuits F are shown coupled to respective inputs ofthe Multiplexer having its common output coupled to the respectiveinputs of the Digital Decision Devices H and I for comparison with +Vand -V reference voltages in a manner like that described above withrespect to the operation of the embodiments of FIGS. la and 1b.

In addition to a respective signal input circuit coupled to thecorresponding output of the impedance matching circuit F of each ofchannels 1 through 11, the Multiplexer of FIGS. 2a and 2b is alsoprovided with a sync input shown coupled to an output of the ADConverter and Digital Control Logic circuitry for receiving a sync pulseto synchronize the operation of the Multiplexer, which functions inresponse to a synchronizing pulse to program or gate the output signalssupplied by the respective channels 1 through n in time sequence, forselectively sequentially coupling the outputs of the respective channelsthrough the Digital Decision Devices H and I to a modified DigitalControl Network J', the details of which are shown in greater detail inFIG. 2c.

The modified Digital Control Network J is substantially identical withthe Digital Control Network and Multiplexer I shown in FIG. lc, exceptfor the Gain Switch Logic portions thereof, e.g. the switch and channeldecode logic. In the Digital Control Network and Multiplexer I of FIGS.la, lb and 1c, the Gain Switch Logic and Multiplexer circuitryincorporates means for performing the multiplexing function in responseto signals from the AD Converter and Digital Control Logic, asindicated. In the modified Digital Control Network I of FIG. 2c, on theother hand, there is no provision for such multiplexing, the latterfunction being performed by a separate Multiplexer, as shown in FIGS. 2aand 2b of the drawing.

In the system of FIGS. 2a, 2b and 2c, the Gain Switch Logic is providedonly with inputs to receive the Switch Counter signals X1, X2 and X3 andis provided with output circuits S1 through S5 each of which, as shownin FIGS. 2a and 2b, is coupled in common circuit to the correspondingswitching element E1 through E5 of the respective channels. Otherwisestated, in the apparatus of FIGS. 2a and 2b, including the detailedshowing of the modified network I illustrated in FIG. 2c, it is seenthat the correspondingly numbered switching networks for all channels 1through n are simultaneously actuated by switching signals from themodified Digital Control Network J. By way of example, a switchingsignal S1 simultaneously actuates switching networks El of channels 1through n, switching signal S2 simultaneously actuates switchingnetworks E2 of channels 1 through n, and so on with switching signal S3,S4 and S5. in turn, simultaneously actuating the corresponding switchingnetworks E3, E4, and E5, respectively, of all channels 1 through n.

In operation, the Multiplexer of FIGS. 2a and 2b, selectively gates onlyone channel at a time to the Digital Decision Devices H and I, andsimultaneously to the AD Converter. Thus, the Multiplexer selectivelygates or passes signals applied thereto from channel 1 during the entireperiod of time when the Digital Control Network J scans through signalsS1 through S5 in order to scan through the channel switching cycle fromswitching network E1 to network E5. Thereafter, allowing time for theSample Hold operation in the AD Converter, the Multiplexer disconnectsthe channel 1 input and selectively passes the output of channel 2 tothe Digital Decision Devices H and I and to the AD Converter for a timeinterval sufficient for the Digital Control Network J again to scanthrough the cycle of switching signals S1 through S5 in order to scanthrough the channel 2 switching cycle switching network E1 to networkE5, and then allowing time for the Sample Hold operation. In likemanner, the Multiplexer, in turn, selectively gates through thesuccessive channels, on through channel n, each channel being `gatedthrough the Multiplexer substantially only for the time intervalrequired by the digital control network J to cycle through switchingsignals S1 through S5, plus the time required to perform the Sample Holdoperation. After the Multiplexer cycles through all channels 1 throughn, as above, the cycle is repeated.

The portions of the circuits shown in one or more of FIGS. la, lb, lc,2a, 2b and 2c, identified as Details A through F, are shown in furtherdetail in FIGS. 3 through 8, respectively. The circuit portionsidentified as Details M through P are shown in FIGS. and 13, as the casemay be, all as discussed above.

In FIG. 3 the elements of the input electronics are shown within thedashed box identified as Detail A having an input coupled to an externalsource of seismic signals shown as a Geophone. In particular, the inputelectronics of Detail A comprises an Input Attenuator having its outputcoupled through a selector switch SW to a high-line balance, identifiedas Hi Line Balance, and to an Input Transformer. The selector switch SW,working in gangedswitch relationship with Detail A Step Gain Control,enables an operator selectively to bypass the Input Attenuator by meansshown as an input by-pass conductor shown coupled between the output ofthe Geophone and the second terminal of the switch SW. The selectorswitch may be of the double-throw-single-pole type for selectivelyconnecting either the Input Attenuator (at switch terminal 1) or theby-pass conductor (at switch terminal 2) in circuit between the detail Ainput, shown coupled to the Geophone output, and the respective inputsof the High- Line Balance and Input Transformer.

The Input Transformer, shown in block form, may comprise appropriateconventional input and output windings, the latter of which is connectedto the input gain stage preamplifier A1. The Input Transformer serves toisolate the Geophone and input cable from the Amplifier A1 andsucceeding circuitry, thereby allowing conventional bridge balancing orcancellation techniques to be used, if desired, to buck out or removesuprious power line i.e., 60 cycle interference due to both inductiveand capacitive effects at the amplifier input. Such unwanted power linesignals may be removed by the high-line balance.

The precision gain stage amplifier A1 is provided to amplify the desiredinput signals sufficiently to overcome undesired input noise level ofactive filters following this stage of gain. These active filters areshown in FIG. 3 coupled to the output of the Amplifier A1 in seriescircuit in the order named. They comprise an adjustable low cut lter(Adj. Lo-Cut Filter) an adjustable high-cut filter (Adj. Hi-Cut Filter),and an adjustable aliasing filter (Adj. Alias Filter). In one embodimentthe input amplifier A1 of Detail A may have a gain of 8.0 overall; orsome other predetermined gain, if the input Cil I6 attenuator isconnected in circuit by positioning the switch SW to switch position 1,as shown in FIG. 3.

Means are provided for adjusting the overall gain of the Detail A inputelectronics portion of the system including a step gain control,identified as Adj Step Gain Sw. in FIG. 3, which can be manuallyadjusted and which, in a preferred embodiment, is also provided withmeans, identified in FIG. 3 as Stage A Gain Logic, for deriving outputsignals in binary form, as shown as Y1, Y2 and Ya, corresponding to theoverall gain of the Detail A input electronics and which binary signalsare coupled by suitable conductors to the Digital Control Network I orJ', as the case may be. In particular, the digital signals correspondingto the Detail A gain level are shown coupled to inputs Y1, Y2 and Y3 ofthe Exponent Adder portion of the Digital Control Network I or I', asshown in FIGS. la and 2a, respectively. The function of the `gain levelsignals is to adjust the Exponent Adder of the Digital Control Network Ior J so that its exponent output signals will automatically be adjustedto take ino accountt the gain level of the input electronics A. In theevent that the input electronics A has a predetermined gain other than8, it may be necessary to provide additional digital signals to or fromthe Exponent Adder, eg., four (4) signal lines to give powers of two (2)or four (4), rather than three (3) as shown for powers of eight (8).

Although the disclosed system includes means for automaticallyintroducing the predetermined gain level of the input electronics A intothe Exponent Adder in order to adjust the exponent signals for theappropriate input electronics gain level, it is also contemplated thatthe Exponent Adder may be adjusted manually, to take into account thepredetermined gain level manually established for the input electronics.It will be appreciated that the overall gain level of the inputelectronics A can be adjusted in known manner, as by the use of asuitable voltage divider (not specifically shown) in the InputAttenuator, in a manner designed to preserve the input impedancethereof, and by appropriate adjustment of feedback (not specificallyshown) within the Precision Gain State A1 in order to adjust the gainthereof. It is further understood that the adjustments of the InputAttenuator and gain of the Precision Gain Stage A1 may be mechanicallysynchronized or ganged. Otherwise stated, the digital gain level signalsderived from the Detail A electronics provides means by which the logicgates comprising the EX- ponent Adder of the Digital Control Network areable to interrogate the Detail A Circuit and adjust the exponent signalsaccordingly in known manner, as indicated in FIG. 3 by the respectivedashed lines from the Input Attenuator and the Precision Gain Stage tothe Adj. Step Gain Sw. comprising the Detail A gain level control.Moreover, the setting or position of the Detail A gain level control canbe readily communicated in conventional manner to the Exponent Adder asby means of appropriate electrical connections indicating the positionof the Adj. Step Gain Sw. together with conventional means, shown as theStage A Gain Logic, for deriving suitable binary cofded signals Y1, Y2and Y3 representative of the setting of the Adj. Step Gain Sw. which, inturn, represents the preset gain level of the input electronicscomprising Detail A. The Detail A portion of each of the respectivechannels 1-n ordinarily should be at substantially the same gain level.Accordingly, the Adj. Step Gain Sw. comprising the gain level adjustmentof the respective channels 1-n will ordinarily be set at the same orcorresponding level and may conveniently be synchronized or ganged, asby appropriate mechanical coupling from one channel level controller toanother. In such event, it will be necessary to provide a Stage A GainLogic circuit in only one of the channels for providing a Detail A gainlevel signal to the Digital Control Logic J or I. Coordination of theDetail A gain level of the respective channels 2-n with that of channel1 is illustrated by the dashed lines connecting the respective Detail Aportions of channels 2 and 1L with the line representing the signalcable carrying the Detail A gain level signals from channel 1 to theDigital Control Network J and I.

In the circuit designated Detail B, as shown in FIG 4, a transistorizedwide band operational amplifier, such as that marketed as the NEXUSSQ-l, is used in a noninverting conguration. The precision gain isdetermined by the precision resistors R1 and R2 of the feedback network.The capacitor C1, shown coupled across the resistor R1 in the feedbackloop, determines the high frequency cut-off point of the cascadednetwork of amplifier stages B1 through B5, shown in FIG. 4a as f2, ofthe amplifier network. The resistor R2, shown D.C. coupling the negativeside of the Operational amplifier to groundV (except for stage B1',shown in FIG. l0 and described in detail elsewhere herein) determinesthe low frequency cut-off point of the amplifier network shown in FIG.4a as f1. In a preferred embodiment, the gain of each one of thecascaded amplifier stages is a constant +8.000 in the pass band down toDC. A balancing adjustment may be provided to correct for input voltagesin the operation amplifier of the Detail B stage, and is shown as anadjustable resistor R3 for DC balancing within the operationalamplifier.

The details of the circuit network designated Detailed C are shownwithin the dashed box of FIG. 5, wherein a limiter circuit is shownwhich clips off the output signal from any preceding stage, thuslimiting the input voltage swing to any following stage to a value suchthat when amplified by a gain of +8.000 (in the illustrated embodiment)the following stage will not saturate. The limiter circuit C comprises aseries input resistance element R4, having its output end coupled to theelectrical mid-point of a pair of diodes, identified as Diode 1 andDiode 2, which, in turn, are coupled in series circuit between anegative source (not shown) of direct current (-D.C.) and a positivesource (not shown) of direct current (+D.C.). This limiter assures thatthe operational amplier will not exceed the linear region of operation.Substantially no distortion will then be found in the onscale amplituderange (i.e. 0.512 volt to 4.096 volts) at the output of the followingDetail B stage. In a preferred embodiment, the signal is limited atabout 0.7+0.1 volt=0.8 volt at the input giving 0.8 8.0=6.4 voltsmaximum at the output of the following Detail B stage. The operationalamplifier of Detail B is capable of swinging its output in a range voltsto -10 volts linearly. The clipping or limiting of the Detail C circuitintroduces distortion during the clip period but not during the loweron-scale amplitude excursions. The first and second diodes shown coupledin series between the -DC and +DC low voltage sources (not shown) arecoupled to precision voltages, supplied from low impedance regulators,having values of 0.7 volt and +0.7 volt, respectively, in the embodimentshown. The midpoint of the first and second diodes is coupled to theoutput end of a resistance element R4 shown coupled in series betweenthe input and output of the Detail C circuit. In a preferred embodimentresistance R4:5.1K ohms. The first and second diodes are capable ofcoming out of conduction quickly, e.g., they have a characteristic fastrecovery. The diodes do not conduct until the input voltage swingexceeds the back bias voltages plus or minus 0.7 volt. At this point, avoltage drop occurs across the resistor R4 due to the diode current fiowand the output remains substantially at plus or minus 0.7+0.l20.8 voltduring the limiting process. It will be appreciated, as suggested above,that a low impedance source of bias voltages, plus and minus 0.7 volt,is required to provide the stiffj e.g., highly stable, bias required.

The circuit designated Detail D, shown within the dashed box of FIG. 6,comprises an operational amplifier connected in a phase invertingconfiguration network to provide a nominal gain of 1.000 with both gainand phase compensation adjustments being provided. The legends in thedrawing describe these functions. A DC balance is required to correctfor the input offset voltage of the operational amplifier and isprovided by an adjustable resistor' R8 within the operational amplifier.A capacitor C2 is provided in series with the input to block DC from theinput stage of the operational amplifier. This capacitor C2 may beeliminated if offset and drift voltages at DC are adequately controlled.Either the inverting or non-inverting version of such an operationalamplifier can be used without a significant change to the function ofthe Detail D stage. A 180 phase inversion is the only difference andthis can be corrected by reversing geophone connections at the inputtransformer, e.g. at the input to Detail A. In a typical embodiment,gain and phase differences between forward paths in any channel can beadjusted to a desired accuracy of 0.1 percent or better regardless ofthe number of gain stages involved. In a forward path from the geophoneto the analog-to-digital converter input, the bandwidth of the overallamplifier path can also be narrowed or adjusted sistors R5 and R7 fromoutput to input shown in Detail D.

The circuit shown in FIG. 6a as Detail D is to be pre` ferred over thatshown in FIG. 6 as Detail D, since it enables significantly betterbandwidth characteristics to be provided for the disclosed system.Details D and D differ in certain respects, including the following:whereas Detail D provides only A.C. gain, Detail D provides both A.C.and D.C. gain; whereas Detail D provides negative gain of unity (-1),Detail D provides positive gain of unity (+1); whereas Detail D includesa phase adjusting network, none is provided for Detail D and none isneeded. Although means are not shown in FIG. 6a for adjusting the D.C.offset of Detail D', it is to be understood that such may be provided bymeans of a balance resistor like R8 of Detail D, shown in FIG. 6. It isnoted that in the ideal case operational amplifiers have zero D.C.offset and should not require D.C. offset adjustment, however, in thepractical case such adjustments may be desirable and can be made throughmeans such as R8.

It will be appreciated that the overall response of the herein describedamplifier system will be substantially flat over a relatively wide rangeextending from a lower frequency close to D.C. up to a high frequencydetermined by the characteristic of the cascade amplifier stages DetailB and, more particularly, by the R1 and C1 components thereof. In atypical embodiment. the R1 may be a value of 35,000 ohms and C1 may be avalue of' 1012 farads (one hundred picofarad) which will provide a highfrequency rolloff at about 40,000 cycles per second. The low frequencyresponse of the amplifier system may be fiat above about three-tenths ofa cycle/second in a typical embodiment. The low frequency response willbe inverse to the roll-off characteristic of the Detail O filter asillustrated in FIG. 12.

The circuit portion designated Detail E is shown within the dashed boxof FIG. 7 wherein there is provided a Low Leakage Switch Elementcomprising a solid state analog switch having a very high offresistance, e.g. low leakage, preferably of the order of ten (10) to thetenth (10th) power ohms and a low on resistance of the order of between30 and 3000 ohms. The solid state analog switch element mayadvantageously be of the field effect transistor type, commonlydesignated FET type. A driver circuit is used to maintain a normally offswitch in the off position. Such a driver circuit is showndiagrammatically as a Switch Driver Stage having its output coupled tothe control input of the solid state switch (FET) and having an input,designated S input (Control input), for receiving digital timing pulsesfrom such as S1, S2, S3, S4 and S5 from the Digital Control Network I orI', as the case may be. As discussed above, in the operation of thedisclosed amplifier systems, such as those illustrated in FIGS. la, 1b,2a and 2b and in other figures hereof, the Switch Driver Stage is usedto control the normally off solid state analog switch element (FET)comprising Detail E and this driver signal is derived from the timinglogic circuitry so that at the proper time it will turn ON the analogswitch element (FET) and hold it on for a given time interval. When theswitch is thus turned ON, the analog signal applied to its signal inputis connected to the output thereof for the given time interval in orderto pass the analog signal in accordance with the desired operatingprogram.

The circuit elements described herein as Detail F are shown within thedashed box of FIG. 8 as comprising an Impedance Transformer having unitygain and being of non-inverting characteristic. For example, a suitableimpedance transformer is shown in the article: A Potpourri of FETApplications, appearing in EDN (Electrical Design News), March 1965,pages 38-45. (See especially: Unity Gain Isolation Amplifier, shown onpage 45.) See also Handbook of Operational Amplifier Applications, page47, Burr-Brown Research Corporation, 1963. The Impedance Transformercomprising Detail F is characterized by an extremely high inputimpedance, preferably of the order of 10 to the 10th power ohms, and avery low output impedance, preferably of the order of 1 ohm. The veryhigh impedance permits the use of a relatively inexpensive eld effecttransistor (FET) switch having a larger on resistance in the precedingDetail E switching network having its respective output coupled to theinput of the Detail F circuit. The input impedance of the Detail Fcircuit should be equal to or greater than 10 to the 7th power times theON resistance of the field effect transistor (FET), such that the ONresistance will not affect the measured precision or accuracy.

While the systems shown in FIGS. la, 1b, 2a and 2b include amplifierchannels comprising five cascaded arnplifier stages, it is to beunderstood that a different number of such stages may be employed inaccordance with the invention. The number of cascaded stages dependsupon the gain per stage and the total gain required to amplify the inputcircuit noise level, just below useable value acceptable to theanalog-to-digital converter coupled to the common output. It isconvenient to use stage gains expressed in powers of two, to be recordedin the binary digit form or system. Thus, with reference to FIG. 9,

seven stages of gain of eight gives a total channel gain` of 2,097,152.It would require twenty-one stages of gain of two to give the same totalgain. Ten stages of gain of four would give a total gain of 1,048,576.An additional stage of gain of two would give the same total gain asbefore.

In a preferred embodiment wherein the A-D Converter is of the binarydigit type it is possible to choose some base comparable to the decimaldecade, such as base eight (8) which is equal to three (3) bits in thebinary system. It is to be understood that the base two (2) could beused but this would increase the complexity of channels considerably forreasons that will be explained further. In a typical seismic signalprocessing system the seismic geophone range of signals may vary fromone (l) volt to one-tenth (0.1) microvolt in the total useable range,i.e., over a 140 db range. Using gain of eight (8) range changes, thiscan be covered in eight (8) amplification steps. Gain of two (2) rangechanges would require twenty-one (2l) steps of amplification, thusincreasing the complexity of channels. A desirable compromise, from theeconomic standpoint, is to choose the gain of eight (8) changes. IIf a15 binary bit A-D `Converter is used, the most significant bit normallyis used for the sign digit giving a bi-polar input capability `while theother' 14 bits express the absolute value of the magnitude of themeasured voltage. As can be seen by the reference to FIG. 9, each timethe input, expressed by the abscissa, drops below full scale by a factorof eight (8) the converter (voltage on the ordinate) reduces fromfourteen (14) to eleven (11) bits and the amplifier gain must beincreased by eight (8) automatically to drive the converter input backup to fourteen (14) bits of measured accuracy. The gain of the amplifierfor each stage output is shown at the top of FIG. 9, along with thestage number or exponent value. The amplifier output or A-D Converterinput is shown on the right in FIG. 9, along with the significant numberof bits, while the db variation below full scale is shown on the leftside of FIG. 9. The input voltage range and its db variations below fullscale are shown at the bottom of the same figure.

The vgain factor is read, e.g., recorded, as an exponent of a suitablebase, the resultant to be multiplied times the mantissa as read by theA-D Converter giving the desired measure of the input signal. Thus, theaccuracy of such a system is equal to or greater than eleven (11) bitsor one part in a thousand, throughout a one hundred forty-four (144) dbinput range for eight cascaded stages and throughout db input range forfive cascaded stages as shown in FIGS. 1a, 1b, 2a and 2b. Reducing theConverter range below eleven (1l) bit accuracy results in a possible 210db total dynamic range of magnitude variation. This increases to 216 dbif the sign digit is considered. Note, as mentioned above, the Voltageread, e.g. the recorded output signal of the system, is an accuratemeasure of the voltage at the geophone terminals. In a practicalembodiment, below an input signal of one-fourth microvolt themeasurement is essentially the noise level of the amplifier input,measured accurately.

In the operation of the disclosed amplifier system large input signalsare soon amplified to a level which would block or paralyze the input ofall succeeding stages. Recovery time constants in the amplifier stageswould preclude measurement of lower level signals immediately followinga large input signal. However, if one deliberately clips off all inputamplitudes greater than fullscale output divided by the gain of thestage so that the output remains in the linear operating range of theamplifier stage one can keep an amplifier channel of n stages operatingin a linear region. This can be done by allowing all limiting to occurin devices known to have very fast recovery times. In this manner thegain in the forward path is not changed and no gain steps occurintroducing transient distortions.

The outputs of a cascaded set of amplifier stages with amplitude limitedinputs will thus be limited to fit the A-D Converter range such that themaximum linear output of any path is slightly greater than full scaleinput for the A-D Converter. By staying in the range of one-eighth fullscale (for gain-of-eight per cascaded stage system) to full scale forthe outputs, and by switching the A-Dy converter to the output of theappropriate amplifier stage, one can stay within three (3) binary bits(18 db) of the A-D Converter full scale value at all times and bemeasuring a portion of the input voltage accurately from one zerocrossing point to the next of the input signal. The only requirement isto be able to switch the cascaded precision gain stage outputsautomatically and at high speeds. No memory is required of previoussample amplitudes as in binary gain amplifier systems. Here eachselected arnplitude is completely independent of all previous ones. Thisis equivalent to having a 36 binary bit A-D Converter sampling thegeophone voltage instantaneously and digitizing it with a guaranteed 11bit accuracy at all times. Since the recorded geophone voltage iswritten in a floating point number form which is ideal for introductioninto digital computers for processing, this amplifier system is referredto as the floating point amplifier system.

It will be appreciated that the above-disclosed signal processing systemprovides means for converting an analog signal to digital words suitablefor recording in a format wherein each digital word occupies a number ofbinary bit positions on a magnetically recorded medium,

